The present disclosures relate to stereophonic audio encoders, and more particularly, to a NICAM processor and method of implementing NICAM processing.
Near-Instantaneously Companded Audio Multiplex (NICAM) encoding improves sound quality and provides multiple channels of digital sound or data compared to other TV sound systems. It is generally used in countries that utilize PAL and SECAM television systems for digital multisound transmission. FIG. 1 is a schematic block diagram view of a prior art composite video and dual channel audio system 10 having an analog filter 12, a dual-channel analog-to-digital converter (ADC) 14, a digital sound NICAM encoder 16, an analog QPSK transmitter 18, and an RF modulator 20. Analog filter 12 filters the two audio inputs 22 and 24, respectively, and outputs the filtered signals on outputs 26 and 28, respectively. The outputs 26 and 28 of analog filter 12 are inputs to the dual-channel ADC 14. ADC 14 receives a first clock at 34 (CLK1), integer multiple of 32 kHz, and converts signals on the ADC inputs 26 and 28 into corresponding digital signals on ADC outputs 30 and 32, respectively. As illustrated, the outputs of the dual channel ADC 14 have 14-bit resolution. Digital sound encoder 16 receives a second clock at 38 (CLK2) and processes signals on encoder inputs 30 and 32 into digitally encoded signals on encoder output 36 according to the NICAM standard. Subsequently, the encoder output 36 is input to analog QPSK transmitter 18. QPSK represents Quadrature Phase Shift Keying. Analog QPSK transmitter 18 receives a third clock at 42 (CLK3) and QPSK modulates the signal received at the input 36 onto the output 40. The QPSK modulated signal on output 40 is then combined with the composite video on signal line 44 by RF modulator 20. The RF modulator then RF modulates the combined QPSK modulated signal and composite video onto RF modulator output 46.
Further in connection with the system of FIG. 1, pre-emphasis can be applied to the two inputs either in the analog or digital domain. The two input signals are digitized to 14 bit resolution at 32 kHz sample rate (CLK1 or an integer divide of CLK1) via ADC 14. The samples are grouped into blocks of thirty-two (32) 14-bit data for the A and B channel, equivalent to a duration of 1 ms. At digital sound encoder 16, the samples of each block are companded to 10 bits with the same scaling factor. One parity bit is then added to each 10-bit sample for error detection and scale-factor signaling purposes. A channel and B channel data are then multiplexed and bits are interleaved according to the interleaving pattern described in the NICAM standard, thus forming a block of 704 bits. Then an 8-bit frame alignment word, 5-bit control information, and 11-bit additional data are added at the beginning of the block of 704 bits, thus forming a frame of 728 bits. Each frame is serially transmitted every millisecond, for example, on signal line 36. The overall bit rate is 728 bit/s, corresponding to clock 38 (CLK2). The bit stream is then scrambled (except for the bits belonging to the frame alignment word), converted into two streams of 1-bit in-phase and quadrature data sampled at 364 kHz (symbol rate), differentially encoded and QPSK modulated, with use of clock 42 (CLK3), onto a 6.552 MHz subcarrier for TV System I or 5.85 MHz for TV System B, G, H and L via QSPK transmitter 18. The QPSK modulated audio signal 40 is then combined with the composite video 44 and RF modulated with RF modulator 20. The RF modulator produces RF signals 46 on VHF and/or UHF channels.
Traditional implementations of NICAM encoding systems are not very cost effective from the view point of integration into an audio/video chip or into a single-chip encoder due to the requirement of multiple clocks and the use of analog blocks which require tuning and which are not easily portable when integrated. Furthermore, traditional implementations of NICAM encoding systems are not very cost effective due to memory requirements and the complexity of the bit interleaving process.
In connection with implementing the NICAM algorithm, memory requirements dictate that the companding process and computation of modified bits can only be performed when all 32 A-channel and B-channel input samples have been acquired. Accordingly, the algorithm requires that 32 samples for each channel A and B must be acquired before performing the NICAM encoding. In addition, a NICAM encoded output stream of 728 bits must be produced continuously without gaps every millisecond. In traditional implementations, extra memory and circuitry are used to meet these requirements. Still further, the interleaving process is complex. The interleaving process according to the NICAM standard is based on a (44×16) matrix structure written by columns, four (4) companded words at a time, and read by rows one bit at a time. In addition, the traditional implementation of a scrambler requires extra processing hardware. As a result, the digital functions of NICAM encoders, in particular, the NICAM algorithm, have been implemented with digital signal processors (DSPs) and Field-Programmable Gate Arrays (FPGAs). Furthermore, pre-emphasis filtering (if not implemented in the analog domain), companding and scale factor encoding are implemented in a DSP, while the NICAM bit interleaving, scrambling and differential encoding are performed by an FPGA. Such DSP and FPGA chips are costly, even when mass produced.
NICAM encoders are generally used in TV stations and typically include very expensive rack mount units. While less costly versions may exist for other applications, the other applications still require a printed circuit board with many discrete components. As a result, in view of cost and complexity, NICAM encoders have been used mainly in broadcast equipment, and not in equipment for use in the home.
Accordingly, there is a need for an improved method for overcoming the problems in the art as discussed above.
The use of the same reference symbols in different drawings indicates similar or identical items. Skilled artisans will also appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.